1. Field of the Invention
The invention relates generally to a method of manufacturing a code address memory (called CAM) cell, and more particularly to, a method of manufacturing a CAM cell by which a stack insulating film of an oxide film and a nitride film used as a dielectric film in a flash memory cell is used as a gate oxide film.
2. Description of the Prior Art
A flash memory cell is used to store an ID of a manufacturing company, a serial number, and the like using a nonvolatile characteristic of a flash memory device. Also, in the flash memory device, in order to prevent deletion of information by unauthorized users, that is, in order to store protection information and un-protection information for protecting a specific memory region in which code information or the like is stored, a CAM cell circuit is inserted into a peripheral circuit region, as shown in FIG. 1.
The CAM cell used for the above purpose is generally used for repair data or protection function. Data must be easily read out from the CAM cell even at a supply power (Vcc) during a normal read operation. The CAM cell, however, includes a flash memory cell used as a main cell.
A method of manufacturing the flash memory cell used as the CAM cell as well as the main cell will be below described by reference to FIG. 2. A tunnel oxide film 12 and a first polysilicon film 13 are first formed on a semiconductor substrate 11. The tunnel oxide film 12 and the first polysilicon film 13 are then patterned to form a floating gate. Next, a dielectric film 14 and a second polysilicon film 15 are formed on the entire surface. At this time, an ONO film in which a first oxide film, a nitride film and a second oxide film are stacked is generally used as a dielectric film 14. A given region from the second polysilicon film 15 to the tunnel oxide film 12 is patterned to form a stack gate in which the floating gate and a control gate are stacked. Thereafter, a source region 16 and a drain region 17 are formed on the semiconductor substrate 11 by means of impurity ion implantation process.
In the above flash memory cell, cells are programmed or erased by charging and discharging electric charges into and from the floating gate In order to perform a read-out operation for finding the program or erasure of the flash memory cell or the state of the flash memory cell, a given voltage must be applied. In other words, as shown in FIG. 3, different levels of a control gate voltage VCG, a source voltage VS, a substrate voltage VB and a drain voltage VD must be applied for respective operations of the flash memory cell.
The above flash memory cell must have a given thickness of the tunnel oxide film and the dielectric film in order to store information for about ten years. In higher-integrated next-generation semiconductor devices, it is difficult to reduce the cell vertically. Therefore, in view of the storage capacity of the cell, it is difficult to increase the current of the cell since it is difficult to form thinly the tunnel oxide film and the dielectric film. As a result, as it is difficult to read information from the main cell using the supply power, it is a general method to read information from the cell by stepping up the gate voltage of the cell using a word line boosting circuit, etc. In case of the CAM cell located in the peripheral circuit, however, there is a problem that the area of the peripheral circuit region is increased because the CAM cell must have additional boosting circuit for this stepping voltage. Also, there is a problem that the device could not be operated without time delay because additional time for reading information is required.
Further, capacitance is generated between respective elements of this flash memory cell. In other words, there are a capacitance Cg between the control gate and the floating gate, a capacitance Cs between the floating gate and the source, a capacitance Cb between the floating gate and the semiconductor substrate and a capacitance Cd between the floating gate and the drain. In order to read out information from the flash memory cell, a coupling ratio being a capacitance Cg between the control gate and the floating gate to the total capacitance must be about 0.55, which lowers the conductance of the cell. Thereby, the operating voltage of the memory device used as a control gate voltage as the threshold voltage of about 2.0V same to the main cell is lowered while the cell current is abruptly reduced, which makes difficult to read given cell information. Therefore, the cell threshold voltage is lowered to abut 0V through over-erasing the cell, thus allowing sensing of data from the CAM cell.
However, the conventional method may over-erase the cell and may thus cause a problem of storing information for a long time due to the leakage current of the cell and the like at various week operating environment such as high temperature or high voltage and the like. Further, in case of this CAM cell, if a manual test is returned to an initial state due to error when the test is performed, the conventional method has a lot of loss in time as the voltage must be lower again.